At FMS 2026, Neo Semiconductor unveiled its dual-transistor (2T) SRAM design, X-SRAM, claiming to achieve five times the on-chip cache capacity of existing...
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At FMS 2026, Neo Semiconductor unveiled its dual-transistor (2T) SRAM design, X-SRAM, claiming to
achieve five times the on-chip cache capacity of existing solutions and increase on-chip SRAM capacity to the GB level. The design includes four cell structures, with the Type B solution directly compatible with the existing GAA Nanosheet logic process. The company also envisions stacked 3D X-SRAM, which is expected to achieve 20~40 times the SRAM capacity of existing designs.
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At FMS 2026, Neo Semiconductor unveiled its dual-transistor (2T) SRAM design, X-SRAM, claiming to achieve five times the on-chip cache capacity of existing...
IT之家(RSS)2026-08-05T01:06:27.000Z
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