NVIDIA 将 Vera CPU 部署于 EDA 流程，加速下一代芯片设计

随着工程团队致力于开发越来越复杂的 CPU、GPU 和 AI 系统，现代芯片设计的复杂性持续增长。为了帮助应对这一挑战，NVIDIA 正与行业领导者 Cadence 和 Synopsys 合作：https://nvidianews.nvidia.com/news/nvidia-expands-nvidia-agent-toolkit-with-nvidia-physicsnemo-and-cuda-x-libraries-to-transform-how-the-world-engineers-designs-and-builds，以优化关键的电子设计自动化（EDA）应用在 NVIDIA Vera CPU 上的性能。

NVIDIA 现在正在将 Vera 部署到用于开发下一代 CPU 和 GPU 的 EDA 工作流程中，展示高性能 CPU 架构如何帮助加速行业中一些最苛刻的工程工作负载。

关键在于芯片生产的速度。进而，受益于增强的 EDA 工作负载的行业技术速度也会提升，从而推动开发势头。

仿真、验证和实现技术在半导体开发中发挥核心作用。在芯片进入制造之前，工程师需要花费多年时间验证行为、识别角落情况并通过成千上万次迭代来优化设计。

尽管 GPU 和 AI 加速了芯片设计的许多方面，但若干关键的 EDA 工作负载仍然高度依赖 CPU 性能。逻辑仿真、形式验证以及部分数字实现通常依赖于快速的单核、有效的内存系统和强大的整体吞吐量。

这使得 CPU 架构成为决定工程团队能够多快验证设计、探索替代方案并将产品推进到流片的重要因素。

NVIDIA 的初步测试包括若干领先的 EDA 应用。结果强调了 Vera 加速现代芯片设计中两个最计算密集阶段的能力。在选定的生产级工作流程上的早期测试显示出令人鼓舞的结果。

Cadence Jasper 是一个形式验证平台，使用智能证明技术和机器学习来查找和修复漏洞，并在设计周期早期提高验证生产力。

Synopsys VCS 是一种高性能功能验证解决方案，用于在制造之前模拟和验证复杂的芯片设计，在测试中使用了相同数量的核心。

在选定的工作负载上，两款应用程序的性能提高了最多 1.5 倍。

除了基准测试结果之外，NVIDIA 还与这两家公司密切合作，进行应用程序分析、软件优化和系统级调优，旨在随着时间推移提升更广泛工作流程的工程生产力。

NVIDIA 正在将 Vera 部署到用于创建未来 NVIDIA 处理器的 EDA 工作流程中。

Vera 结合了 88 个定制的 NVIDIA Olympus CPU 核心、高效的 LPDDR5X 内存子系统以及第二代 NVIDIA 可扩展一致性互联，旨在为高强度工程应用提供强劲的单核性能、高内存带宽和稳定的低延迟。

这些能力对于将延迟敏感作业与大规模回归测试混合在计算集群中运行的工作负载尤其重要。更快的执行速度可以缩短单次验证运行的时间，而更高的吞吐量使工程师能够评估更多设计方案，并在相同开发周期内完成更多验证。

在定义处理器的架构和微架构之后，工程师会在寄存器传输级（RTL）描述其大部分行为。随后，多种验证和实现技术协同工作，将该设计转化为可制造的硅片。

这些工作流程涵盖逻辑仿真、形式验证、回归测试和数字实现，帮助工程师验证功能、识别极端情况，并将设计转化为可制造的硅片。

由于这些阶段相互关联，验证吞吐量的提升可以帮助组织更早发现问题，并减少昂贵的下游设计迭代。

Vera 在 NVIDIA 自身工程工作流程中的部署反映出更广泛的战略：利用最适合任务的计算架构来加速每个工作负载。

在EDA领域，GPU和人工智能继续加速许多算法，而高性能CPU仍然对关键的仿真、验证和实现工作负载至关重要。它们共同帮助提升整体设计周期的性能。

展望未来，NVIDIA计划在Vera的基础上，推出由NVIDIA Rigel核心驱动的下一代Rosa CPU，同时继续优化其CPU路线图上的领先EDA应用程序。

通过使用NVIDIA CPU帮助设计未来的NVIDIA CPU和GPU，公司正在硅设计、软件优化和系统工程之间创建一个持续的反馈循环，每一代都为下一代的发展提供支持。

了解更多关于NVIDIA在DAC 2026的资讯：https://www.nvidia.com/en-us/events/dac/。

The complexity of modern chip design continues to grow as engineering teams work to develop increasingly sophisticated CPUs, GPUs and AI systems. To help meet that challenge, NVIDIA is collaborating with industry leaders Cadence and Synopsys：https://nvidianews.nvidia.com/news/nvidia-expands-nvidia-agent-toolkit-with-nvidia-physicsnemo-and-cuda-x-libraries-to-transform-how-the-world-engineers-designs-and-builds to optimize critical electronic design automation (EDA) applications for the NVIDIA Vera CPU.

NVIDIA is now deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs, demonstrating how high-performance CPU architecture can help accelerate some of the industry’s most demanding engineering workloads.

What’s at stake is the pace of chip production. In turn, the tempo of industry technologies that stand to benefit from boosted EDA workloads, driving development momentum.

Simulation, verification and implementation technologies play a central role in semiconductor development. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations.

While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance. Logic simulation, formal verification and portions of digital implementation often depend on fast individual cores, efficient memory systems and strong overall throughput.

That makes CPU architecture an important factor in determining how quickly engineering teams can validate designs, explore alternatives and move products toward tapeout.

NVIDIA’s initial testing includes several leading EDA applications. The results highlight Vera’s ability to accelerate two of the most compute-intensive stages of modern chip design. Early testing on selected production-class workflows shows promising results.

Cadence Jasper , a formal verification platform, uses smart proof technology and machine learning to find and fix bugs and improve verification productivity early in the design cycle.

Synopsys VCS, a high-performance functional verification solution used to simulate and validate complex chip designs before fabrication, used the same number of cores in the test.

Both applications showed up to 1.5x higher performance on selected workloads.

Beyond benchmark results, NVIDIA is working closely with both companies on application profiling, software optimization and system-level tuning designed to improve engineering productivity across a broader range of workflows over time.

NVIDIA is deploying Vera throughout the EDA workflows used to create future NVIDIA processors.

Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric designed to deliver strong per-core performance, high memory bandwidth and consistent low latency for demanding engineering applications.

These capabilities are particularly important for workloads that mix latency-sensitive jobs with large-scale regression testing across compute farms. Faster execution can shorten individual verification runs, while greater throughput enables engineers to evaluate more design alternatives and complete more validation within the same development window.

After defining a processor’s architecture and microarchitecture, engineers describe much of its behavior at the register-transfer level (RTL). Multiple verification and implementation technologies then work together to transform that design into manufacturable silicon.

These workflows span logic simulation, formal verification, regression testing and digital implementation, helping engineers validate functionality, identify corner cases and transform designs into manufacturable silicon.

Because these stages are interconnected, improvements in verification throughput can help organizations identify issues earlier and reduce costly downstream design iterations.

The deployment of Vera across NVIDIA’s own engineering workflows reflects a broader strategy: accelerate each workload with the compute architecture best suited to the task.

In EDA, GPUs and AI continue to speed many algorithms, while high-performance CPUs remain essential for critical simulation, verification and implementation workloads. Together, they help improve the performance of the overall design cycle.

Looking ahead, NVIDIA plans to build on Vera with the next-generation Rosa CPU, powered by the NVIDIA Rigel core, while continuing to optimize leading EDA applications across its CPU roadmap.

By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next.

Learn more about NVIDIA at DAC 2026 ：https://www.nvidia.com/en-us/events/dac/ .